This invention relates to resistive cross point memory cell arrays and methods of making the same.
Many different resistive cross point memory cell arrays have been proposed, including resistive cross point memory cell arrays having magnetic random access memory (MRAM) elements, phase change memory elements, resistive polymer memory elements, polysilicon memory elements, and write-once (e.g., fuse based or anti-fuse based) resistive memory elements.
A typical MRAM storage device, for example, includes an array of memory cells. Word lines may extend along rows of the memory cells, and bit lines may extend along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line. Each MRAM memory cell stores a bit of information as an orientation of a magnetization. In particular, the magnetization of each memory cell assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of 0 and 1. The magnetization orientation affects the resistance of a memory cell. For example, the resistance of a memory cell may be a first value, R, if the magnetization orientation is parallel, and the resistance of the memory cell may be increased to a second value, R+xcex94R, if the magnetization orientation is changed from parallel to anti-parallel.
In general, the logic state of a resistive cross point memory cell may be read by sensing the resistance state of the selected memory cell. Sensing the resistance state of a single memory cell in the array, however, typically is difficult because all of the memory cells in a resistive cross point memory cell array are interconnected by many parallel paths. Thus, the resistance that is seen at one cross point equals the resistance of the memory cell at that cross point in parallel with resistances of memory cells in the other word lines and bit lines. In addition, if the target memory cell being sensed has a different resistance state due to stored magnetization, a small differential voltage may develop. This small differential voltage may give rise to parasitic or xe2x80x9csneak pathxe2x80x9d currents that may interfere with the sensing of the resistance state of the target memory cell.
Thus, one hurdle that must be overcome before high density and fast access resistive cross point memories may be developed is the reliable isolation of selected resistive cross point memory cells while data stored on a selected memory cell is being sensed. In general, prior techniques for isolating such memory cells fall into one of three memory cell isolation categories: select transistor isolation techniques; diode isolation techniques; and equipotential isolation techniques.
Select transistor isolation techniques typically involve inserting a select transistor in series with each resistive cross point memory cell. This architecture typically is characterized by fast read access times. Unfortunately, such a series transistor architecture typically also is characterized by relatively poor silicon area utilization because the area under the resistive cross point memory cell array typically is reserved for the series transistors and, therefore, is unavailable for support circuits. In addition, this isolation technique also tends to suffer from relatively poor memory cell layout density because area must be allocated in each memory cell for a via that connects the memory cell to the series transistor in the substrate. This isolation technique also generally requires relatively high write currents because an isolated write conductor must be added to the memory cell to provide a write circuit in parallel with a read circuit and the location of the write conductor results in high write currents to generate the required write fields. In general, this approach is limited to a single memory plane because the series transistors must be located in the substrate and there is no practical way to move the series transistors out of the substrate and into the memory cell plane.
Diode isolation techniques typically involve inserting a diode in series with each resistive cross point memory element. This memory cell array architecture may be implemented with thin film diodes that allow multi-level resistive cross point memory arrays to be constructed (see, e.g., U.S. Pat. No. 5,793,697). This architecture has potential for high-speed operation. The difficulty often associated with this architecture involves providing a suitable thin film diode with minimum process feature sizes matching the potential density of the memory cell arrays. In addition, this approach uses one diode per memory element and, at currently practical MRAM features and parameters, for example, each diode would be required to conduct 5 to 15 kA/cm2. Such high current densities generally are impractical for implementing thin film diodes in high-density MRAM arrays.
Equipotential isolation techniques typically involve sensing resistive cross point memory cells without using series diodes or transistors (see, e.g., U.S. Pat. No. 6,259,644). This approach may be implemented by a cross point array of memory elements that is relatively simple to fabricate. This cross point memory cell array architecture typically has a density that is limited only by the minimum feature sizes of the implementing circuit technology and typically requires relatively low write currents. In addition, it is relatively simple to extend this approach to multi: level resistive cross point memory cell arrays to achieve very high-density memories. Equipotential isolation, however, often is difficult to implement in large arrays. Auto-calibration and triple sample read techniques have been used to sense data in large MRAM arrays using equipotential isolation techniques, but these sense processes typically limit the read sense time to a range of 5 xcexcs to 20 xcexcs.
The invention features a data storage device that includes a novel resistive cross point memory cell array that enables high-density fabrication and high-speed operation with isolation diodes that have practical dimensions and current density characteristics. In addition, the inventive data storage device includes a novel equipotential isolation circuit that substantially avoids parasitic currents that otherwise might interfere with the sensing of the resistance state of the memory cells.
In one aspect, the invention features a data storage device that includes a resistive cross point array of memory cells, a plurality of word lines, and a plurality of bit lines. The memory cells are arranged into multiple groups of two or more memory cells. The memory cells of each group are connected between a respective word line and a common isolation diode that is coupled to a bit line.
Embodiments of the invention may include one or more of the following features.
Multiple read circuits preferably are each coupled to one or more associated groups of memory cells by a respective bit line. The read circuits preferably are operable to sense current flow through a memory cell of the associated groups. Each read circuit may include a differential amplifier. The differential amplifier may be a current mode differential amplifier. The differential amplifier preferably is operable to compare current flowing through a selected memory cell with current flowing through one or more reference cells. The data storage device may further comprise multiple comparator circuits each of which is coupled to an associated read circuit. The comparator circuits preferably are operable to convert an analog differential sense voltage to a digital output read signal.
The data storage device preferably comprises an equipotential generator that is coupled to the word lines and the bit lines. The equipotential generator preferably is operable to set voltage levels in the resistive cross point memory cell array to substantially prevent parasitic currents from flowing through unselected memory cells. The equipotential generator may be operable to set an input node of the common isolation diode of each group of memory cells and unselected word lines to a common array voltage. In some embodiments, the equipotential generator is operable to establish equipotential isolation of a selected word line based upon feedback from one or more unselected word lines. Unselected word lines in a selected group of word lines may be connected together to set an averaged feedback voltage that is approximately equal to an applied array voltage. In one embodiment, the input node of each isolation diode is coupled to a respective voltage follower transistor, and the equipotential generator is coupled to gates of the voltage follower transistors. The equipotential generator may comprise an operational amplifier circuit having a first input coupled to a reference voltage, a second input coupled to the word lines, and an output coupled to the gates of the voltage follower transistors. The second input of the operational amplifier circuit may be coupled to the word lines through a switching circuit.
In some embodiments, each memory cell may comprise a magnetic random access memory element.
In another aspect, the invention features a process of making a data storage device. In accordance with this inventive process, a resistive cross point array of memory cells is formed. A plurality of word lines and a plurality of bit lines also are formed. The memory cells are arranged into multiple groups of two or more memory cells. The memory cells of each group are connected between a respective word line and a common isolation diode that is coupled to a bit line.
Other features and advantages of the invention will become apparent from the following description, including the drawings and the claims.